Thyristor semiconductor device and method of manufacture

ABSTRACT

In a method of processing a semiconductor device, a silicide-blocking layer may be formed over a semiconductor material. After defining the silicide-blocking layer, impurities may be implanted into portions of the semiconductor material as defined by the silicide-blocking layer. After the implant, silicide may be formed in a surface region of the semiconductor material as permitted by the silicide-blocking layer. Regions of the impurity implant may comprise boundaries that are related to the outline of the silicide formed thereover. In a further embodiment, the implant may define a base region to a thyristor device. The implant may be performed with an angle of incidence to extend portions of the base region beneath a peripheral edge of the blocking mask. Next, an anode-emitter region may be formed using an implant of a substantially orthogonal angle of incidence and self-aligned to the mask. Epitaxial material may then be formed selectively over exposed regions of the semiconductor material as defined by the silicide-blocking mask. Silicide might also be formed after select exposed regions as defined by the silicide-blocking mask. The silicide-blocking mask may thus be used for alignment of implants, and also for defining epitaxial and silicide alignments.

REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 11/007,510, filed Dec. 7, 2004, now U.S. Pat. No. 7,279,367 which is a divisional of U.S. patent application Ser. No. 10/609,185, filed Jun. 26, 2003, now U.S. Pat. No. 6,888,176, which claims priority to U.S. Provisional Application Ser. No. 60/415,368, filed Oct. 1, 2002, and entitled IMPLANT APPROACH WITH SELF-ALIGNMENT TO SALICIDE BLOCK; All of these applications and patent are hereby incorporated by reference in their entirety.

BACKGROUND

The present disclosure is related to semiconductor devices and their methods of manufacture; and, more particularly, to the devices and manufacture of metal oxide semiconductors and thyristors.

The advancement of the semiconductor industry has brought forward devices of smaller geometries and high density for enabling higher levels of integration. Some of these developments have typically required multiple processing steps and procedures, which can affect their production efficiencies and economics.

A common element in a semiconductor device is a transistor, such as a metal-oxide-semiconductor field-effect transistor (MOSFET). These MOSFETs can be interconnected to other elements on a substrate to form part of an overall electrical circuit such as a memory, a control unit, a network device, a processor or handheld electrical product etc. As the dimensions of these MOSFETs shrink, they can become more vulnerable to source to drain leakage in the semiconductor region under the gate oxide. This leakage can be due to punch through or sub threshold leakage. One method to reduce these leakage mechanisms is to use a Silicon On Insulator (SOI) substrate such as a layer of silicon on oxide where the silicon layer may be thin enough such that a bias of a gate electrode may be capable of fully depleting the silicon layer. Such devices may be described as fully depleted SOI.

One technique that can be used to guard against the breakdown or device degradation from hot carrier injection (HCI) of a gate oxide for a MOSFET is the formation of drain/source extension(s), known alternatively as lightly doped drain (LDD) regions. These regions can be formed in an upper surface region of the semiconductor material and/or with lighter doping than the source drain regions of the MOSFET and may extend laterally beneath the gate and between the channel and their respective source and drain regions. For example, such devices may comprise relative concentration differences as may be presented by S/D regions of concentrations in the Xe20 range, LDD regions with concentrations from about Xe18 to Xe19 and channel regions with concentration of about Xe17. During operation of such MOSFET, the resistance of the extension regions can provide voltage drops along their length that may be sufficient to enable the MOSFET to withstand higher voltage operation.

Another contribution to the evolution of smaller geometry devices has been the advent of silicon-on-insulator technology. MOSFETs formed on conventional Silicon-on-insulators (SOI) exhibit lower parasitic junction capacitance, greater on/off isolation and better sub-threshold swing in comparison to their equivalent bulk counterparts. With these performance advantages, the SOI devices can perform with lower power, higher speed and improved switching characteristics.

For SOI MOSFETs, it may be desirable to form a thin silicon layer for the channel regions so that the channel region may be fully depleted. At the same time, there may be an opposing desire, to enhance the thickness of their source and drain regions for lower resistance. The thicker the source drain regions the thicker the salicide layer formed on them can be. The thicker the salicide layer the lower the salicide resistance. To accommodate these dual objectives for a thin channel region and thicker source drain regions, raised structures may be formed over the source/drain regions. These raised source and drain structures may be formed through either the use of epitaxial deposition or trench formations for recessed gates. By elevating the source and drain regions, metal diffusion during silicide formation need not consume their full thickness. Typically the silicide, epitaxial deposition and implant processes might each be performed using separate patterning provisions. They may be patterned for placing silicide and/or epitaxial material offset from the source/drain extension regions. By such offset, manufacturing tolerances may be accommodated during their fabrication such that the silicide and/or epitaxial material might not overlap the extension regions. Accordingly, it may be noted that an overall length of a MOSFET could thus be limited by the manufacturing tolerances of the various mask patternings associated with the separate silicide, epi and/or implant masks.

In the case of fabricating thin capacitively coupled thyristor (TCCT) devices, there may be a need to silicide the anode/cathode-emitter regions. Additionally, an electrode over one of the base regions might need to be formed with an offset relative to its other base region. Such offset may allow operation of the electrode with reduced likelihood of gate induced leakage (GIDL) effects relative to the offset base region. Typically, fabrication of the offset base might require separate masking provisions to assure its offset relationship relative to the gate electrode. Additionally, silicide patterning might also use its own masking provisions for forming the silicide with clearance from the electrode and the base regions. For if the salicide were to overlap two thyristor regions, the shorting by the silicide could destroy thyristor operation.

It may be noted that these separate patterning and masked provisions for the source/drain extensions, silicide and/or epi structures for a MOSFET, may each add to the complexity, cost and size of the overall device. Likewise, it may be noted, that the separate mask provisions for definition of the offset base, the emitter silicide and/or the epi structures for the thin capacitively coupled thyristor may similarly add to its overall complexity, cost and size.

SUMMARY

In accordance with embodiments of the present invention, dielectric may be patterned as a mask and may be used repetitively for defining source/drain extension regions for a MOSFET and also for defining silicide and/or epitaxial structures.

In other embodiments, the formation of a capacitively coupled thyristor may similarly use a common mask for defining a base region silicide, epitaxial structure and/or leakage implant.

In one embodiment, a semiconductor device may comprise silicide disposed on a layer of semiconductor material. Impurities may be formed in a region of the layer of semiconductor material. The silicide over the layer of semiconductor material may comprise an outline related to patterning of the impurities. In a further embodiment, the silicide may have a peripheral edge that is aligned with relationship to a lateral extent of a doped region defined by the patterning of the impurities.

In a further embodiment, a shallow implant extension region may be formed in a layer of semiconductor material in contiguous relationship with a deep level implant region. The interface therebetween may define an outline that is related to the peripheral edge as defined for the silicide.

In accordance with yet a further embodiment, a semiconductor device may further comprise a gate electrode over the layer of semiconductor material and a silicide blocking material on a region of the semiconductor material between the silicide and the gate electrode. The silicide blocking material may extend laterally outward from the gate electrode to meet a peripheral edge of the silicide. The silicide blocking material may protect a surface of the shallow implant region and a portion of the deep level implant across the interface with the shallow implant region.

In another embodiment, a transistor comprises source and drain regions of first conductivity type with a channel of second conductivity type between the source and drain regions. A gate electrode may be disposed over the channel region and operable under bias to affect an electric field in the channel region. At least one source and drain extension region of first conductivity type may extends laterally between the source/drain region and the channel region. The source/drain region may comprise dopant of the first conductivity type and may be contiguous with its respective extension region. In particular embodiments, the source/drain region may be more heavily doped than the extension region. Further, the source/drain region may be offset laterally from the outline of the gate electrode and the silicide thereover may comprise a peripheral edge that is laterally offset from a boundary between the source/drain region and the extension region. In a particular embodiment, a peripheral edge of the silicide meets a surface of the source/drain region and a spacer might also be formed against a sidewall of the gate electrode to serve as a silicide-blocking layer. Such silicide-blocking layer may be disposed with a lateral extent over the extension region.

According to another embodiment, a method of processing a semiconductor device may comprise patterning a silicide-blocking layer over semiconductor material. After implanting a select region of the semiconductor material, a metal may be formed over exposed regions of the semiconductor material and a portion of the metal diffused into a surface layer of the semiconductor material as defined by the patterned silicide-blocking layer. In a particular embodiment, the implanting may comprise a first implant to place first impurities into a first region of the semiconductor material and to define a thyristor base region in accordance with patterning of the silicide-blocking layer. The implanting might also comprise a second implant to place second impurities into a second region of the semiconductor material to define an emitter region of the thyristor next to the base region. The extent of the first region may be defined by the patterned salicide-blocking layer and at least one of the implant energy, implant angle, and species of implant associated with the first impurities. The second region may be defined by the patterned salicide-blocking layer and at least one of the implant energy, implant angle and species associated with the second impurities implant. At least one of the implant energy, implant angle and species of the second impurity implant may differ from that of the first impurities implant. This may result in the implant or implants being self aligned to the salicide blocking material.

In a further aspect, the implant for the first impurities may comprise an angled implant to implant regions of semiconductor material beneath a portion of the patterned salicide blocking layer. Additionally, a substantially orthogonal implant may be used for the second impurities implant.

In a further aspect, the first region of the first implant species may be defined to extend laterally in the layer of semiconductor material to a position beneath the salicide blocking layer but laterally clear of the region beneath the outline of the gate electrode.

In accordance with another embodiment of the present invention, a semiconductor device may comprise a layer of semiconductor material with a plurality of regions of alternating first and second opposite conductivity-types disposed therein. One region of the plurality of regions comprises an anode-emitter and another region may comprise a cathode-emitter. The cathode-emitter may comprise an N-type conductivity and the anode-emitter may comprise a P-type conductivity. At least two regions of the plurality of regions may be disposed between the anode-emitter and the cathode-emitter. The anode-emitter may define a junction where it meets one of the at least two regions. A first electrode may be disposed over at least one of the regions between the anode and the cathode-emitters. Epitaxial material may be disposed over one of the cathode-emitter and/or anode-emitter regions and may be offset laterally clear of the junction of the anode and/or cathode-emitter region(s) at the surface of the layer of semiconductor material.

In another embodiment, the anode-emitter, the cathode-emitter, and the at least two different regions of alternating regions therebetween define a thyristor having a surface region thereof that is free of silicide between a peripheral edge of the epitaxial material over the anode-emitter and a peripheral edge of the first electrode. The silicide free surface may further overlap a full-width of the first base region and the second base region.

In another embodiment, the semiconductor device may comprise conductive material to propagate a reference voltage to at least one of the anode and cathode-emitters.

In accordance with another embodiment, a memory device may comprise a thyristor formed in a layer of semiconductor material. The thyristor may comprise an anode-emitter, a cathode-emitter, and first and second base regions between the anode-emitter and the cathode-emitter. A first electrode may be disposed over and capacitively coupled to at least a portion of the first base region. The second base region may be offset laterally clear of the first electrode. A raised provision of semiconductor material may be disposed on the layer of semiconductor material and at least one of the anode and cathode-emitters. The raised portion of the anode-emitter may comprise an outline spaced laterally clear from the first base region.

In accordance with another embodiment, a method of forming a thyristor memory device may comprise forming a wordline over a layer of silicon. A conformal layer of silicide blocking material may be formed over the wordline and the layer of silicon and patterned to define a salicide mask comprising a first part over at least a portion of the wordline, a second part contiguous with the first part and conformal to a sidewall of the wordline, and a third part contiguous with the second part as a shoulder that extends outwardly from the wordline and across a portion of the layer of silicon that neighbors the wordline. Dopant of a second type conductivity may be implanted into select regions of the silicon using an acute angle of incidence to penetrate peripheral regions beneath the salicide mask. After the implanting with the second type conductivity dopant, first type conductivity dopant may be implanted in the layer of silicon using a substantially orthogonal angle of incidence to penetrate regions self-aligned with the salicide mask.

BRIEF DESCRIPTION OF THE DRAWINGS

Subject matter of embodiments of the present invention and methods of fabrication may be understood by reference to the following detailed description when read with reference to the accompanying drawings, in which:

FIG. 1 is a cross-sectional view of a portion of a semiconductor view device during a method of fabrication according to an embodiment of the present invention, showing two separate electrodes over different active regions of the semiconductor substrate.

FIG. 2 is a cross-sectional view of a portion of the semiconductor substrate of FIG. 1 in another stage of processing, useful to further describe a method of fabricating the semiconductor device and showing deep level source/drain implants about a gate electrode.

FIG. 3 is a cross sectional view of a portion of the semiconductor substrate of FIGS. 1 through 2, in another stage of processing and useful to further describe the method of forming the semiconductor device in an embodiment of the present invention, and showing implants about a gate electrode associated with another active region.

FIG. 4 is a cross sectional view of the portion of the semiconductor device of FIGS. 1 through 3, in another stage of processing and useful to further describe the method of forming a semiconductor device in accordance with an embodiment of the present invention, and showing the silicide in exposed regions of silicon as defined by a silicide blocking mask.

FIG. 5 is a cross sectional view of a portion of a semiconductor device and useful to further describe an alternative method of processing of the present invention, and showing extension regions about a gate electrode of an access transistor to a thyristor memory.

FIG. 6 is a cross sectional view of a portion of a semiconductor device of FIG. 5, in another stage of processing a thin capacitively coupled thyristor and showing implants for at least one of the N-base and one of the anode/cathode-emitters.

FIG. 7 is a cross sectional view of a portion of a semiconductor substrate of FIGS. 6 and 7 in another stage of processing useful to further describe a method of forming a thyristor memory, and showing salicide formed over exposed silicon regions.

FIGS. 8A through 8E are cross-sectional views of a portion of a semiconductor substrate during a method of forming trench regions within an SOI semiconductor device, which may be used in a method of forming a semiconductor device of the present invention.

FIG. 9 is a cross sectional view of a portion of a semiconductor substrate illustrating a thyristor memory comprising gate electrodes recessed within trenches of an SOI substrate.

FIG. 10 is a cross sectional view of a portion of a semiconductor device illustrating a thyristor memory of another embodiment of the present invention and showing raised source/drain regions and silicide in alignment with a silicide-blocking material.

FIG. 11 is a cross sectional view showing a portion of a semiconductor substrate during another method of processing a thyristor memory, and showing leakage implants overlapping an interface between an anode-emitter and base region.

FIG. 12 is a cross sectional view showing a portion of a semiconductor substrate in a stage of processing useful to further describe a method of forming a thyristor memory of another embodiment, and showing a thickened spacer to assist implant of a base region.

FIGS. 13A through 13B are cross sectional views showing a portion of a semiconductor substrate in two different stages of processing useful to describe a method of fabricating a thyristor memory in accordance with an alternative embodiment of the present invention, and showing a sacrificial element to define patterning of base region and to affect alignment of impurity lifetime adjustment species.

FIG. 14 is a cross sectional view of a portion of a semiconductor substrate during a method of forming a thyristor memory according to another embodiment of the present invention, and showing leakage implant species across an interface between an emitter and base of the thyristor.

FIG. 15 is a cross sectional view showing a portion of a semiconductor substrate during a method of processing a thyristor memory in accordance with yet another embodiment of the present invention, and showing an isolation trench exposing end portions of an emitter and base.

DETAILED DESCRIPTION

In the description that follows, numerous specific details may be set forth to provide an understanding of exemplary embodiments of the present invention. It will be understood, however, that alternative embodiments may comprise sub-combinations of the disclosed examples.

Additionally, readily established circuits and procedures of the exemplary embodiments may be disclosed in simplified form (e.g., simplified block diagrams and/or simplified description) to avoid obscuring an understanding of the embodiments with excess detail. Likewise, to aid a clear and precise disclosure, description of known processes—e.g., formation of sidewall spacers, photoresist and mask patterning, etc.—may similarly be simplified where persons of ordinary skill in this art can readily understand their structure and formation by way of the drawings and disclosure. For the same reason, identical components may be given the same reference numerals, regardless of whether they are shown in different embodiments of the invention.

As used herein, “substrate” or substrate assembly may be meant to include, e.g., a portion of a semiconductor wafer. Such portion may have one or more layers of material including, but not limited to Si, Ge, SiGe, and all other semiconductors that have been formed on or within the substrate. Layered semiconductors comprising the same or different semiconducting material such as Si/Si, Si/SiGe and silicon-on-insulator (SOI) may also be included herein. These layers and/or additional layers may be patterned and/or may comprise dopants to produce devices (e.g., transistors, diodes, capacitors, interconnects, etc.) for an integration of circuitry. In forming these devices, one or more of the layers may comprise topographies of various heights. When referencing this integration of circuitry, therefore, it may be described as integrated together, on or with the substrate.

Furthermore, those skilled in the art will recognize that although embodiments of the present invention may describe fabrication of an N-type MOS transistor, the dopant type(s) of the substrate in addition to the doped regions thereof may be reversed to form a P-type MOS device. In addition, and in accordance with further embodiments, both N-type and P-type devices may be formed on the same substrate as part of a combined CMOS process.

Likewise, a thyristor may be described with a particular order of anode-emitter, N-base, P-base and cathode-emitter with the anode-emitter attached, e.g., to a reference voltage and perhaps the cathode-emitter in common with a source/drain region of an access transistor. It will be understood that other embodiments may comprise an alternative order of the thyristor or change of NMOSFET devices to PMOSFET. For such alternative polarity embodiments, the cathode-emitter might be coupled in a reference voltage and the anode-emitter coupled to an access transistor.

As referenced herein, portions of (e.g., a transistor or thyristor) may be described as formed in, at or on a semiconductor substrate. Such alternative terms in/at/on may be used individually merely for purposes of convenience. In the context of forming semiconductor devices, such terms may collectively reference portions of a semiconductor element that may be within and/or on a starting material.

In accordance with an embodiment of the present invention, with reference to FIGS. 1 through 4, a method of processing a semiconductor device may comprise forming first and second active regions 22,24 in semiconductor substrate 10. An isolation trench 12 may be formed to define a boundary between the first and second active region(s). In a particular embodiment, the semiconductor substrate 10 may initially comprise a P-type semiconductor material 21 and the first active region 22 may be defined by implanting N-type dopant for well 20 within the semiconductor material of substrate 10. The patterning and definition of the “N” well for the first active region 22 may be performed using standard photolithographic patterning techniques.

Next, further referencing FIG. 1, a dielectric such as an oxide may be formed over substrate 10 and may be described as a gate oxide for different gate stacks that may be formed thereover. After forming dielectric 16A, 16B, poly may then be deposited, doped and patterned in to define gate electrodes 14A, 14B in insulated relationship over respective active regions 22,24.

Next, further referencing FIG. 1, one of the first or second active region(s) 22,24 may be masked with photoresist while processing the other active region for defining devices therein. For example, active region 22 may be masked while pattering N-type, extension regions 30,32 about gate electrode 14B. Additionally, halo implants might also be provided around gate electrode 14B between the extension regions 30,32 and the respective channel region. In a particular embodiment, these halo implants may comprise, e.g., boron implanted with an implant angle of about 35 degrees, energy of 65 keV, and dosage of 2×10¹³ per centimeter squared.

In one example, the gate oxide may be formed with a thickness of 10 nanometers, the polysilicon for the gate with a thickness of 200 nanometers and the implant for the extension regions may be formed using phosphorous of an implant dosage of 8×10¹⁴ per cm².

Although, particular levels and thicknesses may be disclosed for a particular embodiment to forming N-channel devices over active region 24, it will be understood that these parameters are merely exemplary and that alternative geometry's for oxide thickness, implant species or densities may be used for defining devices of alternative specifications. For example, in another example, the oxide thickness for the gate stack might comprise a thermal oxide of 2 nanometers and the N-type extension species of arsenic that may be implanted with a 7 degree angle and an energy level of 5 keV with a dosage of 8×10¹⁴ per centimeter squared. In some cases, the extension regions may be references as lightly doped drain (LDD) regions; however, it may be noted that the dopant concentration of the extension regions may be very close to that of the source/drain regions.

After defining the N-type, extension regions of the second active region 24, it may then be masked while forming P-type extension regions in the first active region 22. The P-type extensions may be formed using, e.g., boron with an implant angle of less than 7 degrees, implant energy of 4 keV and dosage of 4×10¹⁴ per centimeter squared. Additionally, halo implants may be formed using an arsenic dopant of an implant angle of about 45 degrees, energy of 120 keV and dosage of 2×10¹³ per centimeter squared.

After defining the extension regions (and/or Halos) for the N/P-type MOSFET devices over the respective active regions 24,22, the process flow may continue with definition of the P+ and N+ source/drain regions, typically of greater depth and, in some embodiment, of greater dopant concentrations. Referencing FIG. 2, dielectric 34 may be layered conformally over substrate 10 and gate electrodes 14A,14B. In a particular embodiment, dielectric 34 may comprise a material appropriate for blocking diffusion of metal atoms, as might otherwise occur during formation of silicide into an upper region of a silicon layer of the semiconductor substrate. Likewise, dielectric 34 might also be used to block epitaxial deposition in further embodiments of the present invention.

Continuing with this particular embodiment with further reference to FIG. 2, photoresist 36 may be layered over substrate 10, electrodes 14A,14B, and the conformal layer of dielectric 34. Photoresist 36 may then be patterned to facilitate patterning of the dielectric to define mask 34′ and to expose regions 33 of semiconductor substrate 10.

In accordance with a particular embodiment, it may be understood that the dielectric material of layer 34 may be removed by an anisotropic etch and as defined by patterned photoresist mask 36A. Alternatively, the exposed region of the dielectric material 34 may be removed by an anisotropic etch.

Using the patterned dielectric 34′ and photoresist 36A,36B as an implant mask, P-type dopant 38 may be implanted into regions 40,42 of semiconductor substrate 10 for defining the greater density and depth P+ regions for the source/drain regions of a P-MOSFET device. In this particular embodiment, the dielectric patterned mask 34′ may comprise a shoulder 35 that extends laterally outward from gate electrode 14A that may also be used to define a length of the extension region 28′ via the self-alignment of the higher energy P-type dopant 38.

After defining the P+ regions for the P-channel MOSFETS over active region 22, the process flow may continue with definition with mask patterning 44A,44B for similar but opposite polarity-type processing over the other active area 24 of the substrate shown in FIG. 3. Again, exposed regions of dielectric 34 may be removed by one of either an anisotropic or isotropic etch to define mask 34″ and to expose regions 37 of the semiconductor material. N-type dopant material may then be implanted for defining the deep level N+ regions 48,50 of respective source/drain regions of the N-MOSFETS. In a particular embodiment, the deep implants for the N+ regions 48,50 may be formed using implant species such as arsenic with an implant dose of 2×10¹⁵ and energy of about 40 keV.

Further referencing FIG. 3, dielectric material 34 may be patterned in accordance with photoresist mask 44B to define mask 34″ with a shoulder that extends laterally outward from gate electrode 14B. The lateral extent of this shoulder may define an extent of the extension region between gate electrode 14B and the interface to the deep level N+ implant 48.

Moving forward with reference to FIG. 4, after defining the N+ and P+deep level implants for the respective N and P channel MOSFET devices, photoresist 44 may be removed. While using the dielectric patterns 34′ and 34″ with shoulders that extend laterally outward from their gate electrodes and over the respective lengths of the extension regions 28′ and 32′, metal such as at least one of tungsten, nickel, cobalt, platinum, titanium or other refractory metal may be deposited over the masked substrate. A heat treatment may then diffuse metal into the exposed regions of semiconductor material 10 and also any exposed regions of the polysilicon gate electrodes. The exposed regions may be defined by the masks 34′ and 34″ and spacers 29′,29″. After diffusing the metal into the exposed regions of semiconductor material, an acid bath may be used to strip unreacted portions of the metal to leave silicide 52,54 on the deep level implant regions of MOSFET devices and on the gate electrodes respectively. The outline of the deep level implants may be aligned at least in part relative to the patterning of silicide structures 52. This may be alternatively disclosed as defining a boundary of the deep level implants and respective source/drain extensions in alignment with the outlines of the silicide thereover.

After siliciding the exposed regions of semiconductor material, processing of the semiconductor device may be performed in typical fashion for interconnecting the different transistors with other elements of the semiconductor substrate. Through such processing, insulating materials may be formed over the structures and appropriate conductive interconnects patterned to respective contacts of the various gate and/or source/drain regions to form part of an integrated circuit.

In accordance with another embodiment of the present invention, with reference to FIGS. 5 and 6, a method of forming a thin capacitively coupled thyristor may employ use of a silicide-blocking mask for definition of multiple features of the thyristor device. As shown in FIG. 5, a layer of semiconductor material 60, such as silicon, may be formed over an insulating layer 58 such as an oxide to provide a substrate 56. The substrate might further comprise additional supporting structures (not shown). In a particular embodiment, the layer of semiconductor material 60 may comprise silicon of a depth of less than 100 nanometers, and more typically, less than 50 nanometers. Such substrate structure 56 can be described as a silicon-on-insulator (SOI) substrate.

As described earlier relative to FIG. 1, dielectric 63 such as an oxide may be formed over semiconductor material 60 to define, for example, a gate oxide. After forming the gate oxide, poly may be deposited and patterned to form electrodes 62 and 74 over the gate oxide 63. Electrode 62 may be formed above regions for a MOSFET by which to access the thyristor. Electrode 74 may be formed over a base region of a thyristor to be capacitively coupled thereto. As referenced subsequently herein, gate electrode 62 and capacitor electrode 74 may be described alternatively as wordline one and wordline two or first and second wordlines respectively.

With further reference to FIG. 5, after patterning the first and second wordlines 62 and 74, dielectric may be formed conformally over substrate 52 and the electrodes 62,74. Next, photoresist may be layered over dielectric 64 and patterned to define photoresist mask 71 thereover. In this particular embodiment, photoresist mask 71 may define exposed regions of dielectric over a portion of second wordline 74, all of first wordline 62 and regions of the semiconductor material about first wordline 62.

After patterning photoresist mask 71, the exposed regions of the dielectric may be etched by an anisotropic etch. The anisotropic etch may be selective for etching the dielectric more favorably relative to semiconductor material 60. The anisotropic etch may be stopped after exposing poly of wordlines 62, 74 and silicon of the semiconductor material 60 between the first and second wordlines. By such anisotropic etch, dielectric spacers 64′ may be defined about sidewalls of first wordline 62 and against a sidewall of second wordline 74 proximate the first wordline. It may be noted that the width (or thickness) of the sidewall spacers 64′ may comprise a magnitude comparable to the original thickness of the dielectric layer 64.

After forming the first and second wordlines 62, 74 and typically before layering the dielectric material 74, the extensions 72 may be formed about wordline 62, similarly as described earlier herein relative to FIG. 1. For example, they may be formed with a dopant of arsenic using an implant angle of approximately 0 degrees, dosage of 8×10¹⁴ and energy of about 5 keV. Additionally, photoresist masking may be used to block regions of semiconductor material 60 on a side of the second word/line 74 opposite to that of the first wordline 62 during the formation of extensions 72.

In addition, halo implants may be provided, as known in the art, proximate the extension regions 72 and near the channel regions beneath the first word/line 62. After forming the extensions and/or the halo regions for the access transistor 73, dielectric layer 64 might then be deposited as a conformal layer as referenced earlier herein to cover the substrate by which to form the sidewall spacers 64′.

After sidewall spacers 64′ have been formed against sidewalls of first wordline 62 and the sidewall of second wordline 74 proximate the first wordline, N-type dopant 68 may be implanted using species, energy and dosages for definition of the deeper and higher density source/drain regions 84 and 86 (referencing FIG. 6) about the first wordline 62. It may be seen that these deep level implants 84,86 may penetrate the full depth of semiconductor material 60 associated with SOI substrate 56. Additionally, deep level implants 84,86 in combination with the shallow level implants 72 (FIG. 5) proximate the channel 90 beneath gate electrode 62 and may define, at least in part, N-MOSFET device 73. In operation, by applying a bias to gate electrode 62, a conductive channel 90 may be defined between the source drain regions of the N-channel MOSFET to allow access to the thyristor. Subsequently herein, the N-channel MOSFET device may be described alternatively as access transistor 73.

Moving forward with further reference to FIG. 6, another photoresist mask 76 may be formed over the substrate and may comprise a portion thereof over a shoulder 35 of the dielectric layer extending laterally outward from the second wordline 74 and on a side thereof opposite to first wordline 62. The lateral extent for shoulder 35 may comprise a distance that is greater than the conformal thickness of the dielectric material, and sufficient for forming an N-base region therebelow and laterally offset from a peripheral edge 94 of the second electrode 74. After defining sidewalls 78 of photoresist 76 to expose regions of the dielectric, an etch, such as an anisotropic etch, may be used to remove the exposed portions of dielectric and to expose portions 80 of the semiconductor material 60. The anisotropic etch, in turn, may define dielectric mask 64″ over a portion of second wordline 74, extending along a sidewall 94 of the wordline opposite to the first wordline and extending laterally outward therefrom over a portion of semiconductor material 60.

In accordance with one embodiment of the present invention, photoresist 76 in combination with patterned dielectric mask 64′ may be used together as an implant mask for definition of N-base 98 and also for definition of anode-emitter region 100. As used herein, it will be understood that the anode-emitter of the thyristor could be formed with opposite dopant to provide the cathode-emitter. Likewise, the cathode-emitter of the thyristor could be formed with opposite conductivity type to provide the anode-emitter.

Further referencing FIG. 6, in the present embodiment, N-base 98 may be formed using an implant species such as phosphorous with an implant angle of about 45 degrees, an implant dose of 5×10¹⁴ per cm² and energy of about 70 keV. It will be understood; that the implant species, angle and energy in combination with the lateral extent of the implant mask 64″ may be controlled to implant the impurity species for establishing an extent therefore beneath shoulder 35 of dielectric 64″ and, at the same time, offset from edge 94 of second wordline 74. Being offset from the second wordline, N-base 98 may be able to avoid gate induced leakage affects with respect to second wordline 74. After implanting N-base 98, the same mask 64″ may be used during implant of P-type impurities to define anode-emitter region 100, to complete primary portions of thyristor 102A. During implant of the P-type dopant, an implant species such as boron may be used with an implant angle of less than about 4 degrees at a dosage of about 5×10¹⁵ per centimeter square and implant energy of about 10 keV.

Further referencing FIG. 6, it may be understood that mirrored elements of thyristor 102 and access transistor 73 may be formed in the substrate about mirror access 104.

After defining N-base 98 and anode-emitter 100, photoresist 76 may be removed. Moving forward with reference to FIG. 7, metal comprising at least one of the group consisting of cobalt, titanium, tungsten, platinum, nickel, or other refractory metal may be formed over the substrate including wordlines 74,62 and mask elements 64′,64″. A heat process may then be performed using a temperature sufficient to cause the metal to react with the silicon but low enough that no metal/dielectric (64) reaction occurs. Metal may diffuse into the surface of the exposed portions of substrate 60 and also into the surface of the exposed portions of polysilicon of gate electrodes 62,74. After such silicide formation, remaining metal may be removed using, e.g., an acid bath, leaving salicide over anode-emitter 100 that is self-aligned relative to mask 64″. Silicide may also be formed over a portion of the second wordline between dielectric mask 64″ and its sidewall spacer 64′. Additionally, silicide 114 may be formed over the cathode-emitter region 84 between spacers 64′ of the adjacent electrodes 62,74 and silicide 116,118 also on top of the first wordline 62 and also over source/drain region 86 of the access transistor 73. After siliciding the exposed silicon regions, subsequent processing may be formed as known to provide electrical contacts to the anode-emitter, wordlines and bitline contacts for enabling electrical interfacing and operation of the thyristor memory cell 700.

In accordance with an alternative embodiment of the present invention, the definition of N-base 98 and anode-emitter 100 may be performed prior to performing the deep level source/drain implants about access transistor 73. For example, after defining a peripheral edge 96 of the dielectric material layer 64, and after implanting N-base 98 and anode-emitter 100, photoresist may be formed over these regions while leaving other areas exposed to allow formation of spacer 64′ adjacent the wordlines. Implant of the deep level drain/source regions 84,86 of the access transistor 73 might then be performed. In other words, deep level implants 84,86 for the access transistor may be established either before or after formation of the N-base 98 and anode-emitter 100 for the thyristor device 102A. Again, it may be seen that the extent 99 of N-base 98 beneath the shoulder 35 of the dielectric mask 64″ may be defined at least in part by an outline associated with patterning of silicide 110. Additionally, it may be seen that extent 99 is offset laterally from the peripheral edge 94 of second wordline 74. Subsequently herein, extent 99 may be referenced alternatively as interface 99.

In a further embodiment, an additional lifetime adjustment implant may be performed across the interface 101 between the anode-emitter 100 and N-base 98 such that the impurity lifetime adjustment species effect leakage properties of the interface 101 therebetween, but not interface 99 between N-base 98 and P-base 82. In accordance with such embodiment, the implant species, energy level and angle of incidence may be selected such that the lifetime adjustment species overlaps the interface 101 between anode-emitter 100 and N-base 98, but not across the interface 99 between the N-base and P-base. Examples of such lifetime adjustment species may include impurities such as germanium, metal, or inert gas, of a damage type implant. Further information regarding lifetime adjustment species may be found in may be found in U.S. Pat. No. 6,462,359 entitled “Stability In Thyristor-Based Memory Device” of Nemati et al., hereby incorporated by reference in its entirety.

In accordance with a further embodiment of the present invention, skipping forward with reference to FIG. 9, an alternative thyristor and access transistor configuration of a thyristor memory device 900 may comprise capacitor electrode 274 and gate electrode 262 recessed in trenches, which may be used to reduce the thickness of the silicon regions 282 and 288 beneath the electrodes. This alternative structure 900 can be contrasted with the configuration of thyristor memory device 700 as shown in FIG. 7. In this particular embodiment, the SOI substrate 56 may comprise silicon of about a 100-nanometer thickness over buried oxide 58. The trench formations, in which to form electrodes 262,274, may reduce the silicon thickness at their floors to a thickness of about 30 nanometers. Other than the trench structures, formation of the thyristor memory cell 900 may essentially follow the processing procedures as may be outlined herein relative to other thyristor memory devices such as device 700 of FIG. 7. Regarding the trench structures, they may be formed by a process as described below with reference to FIGS. 8A through 8E.

Referencing FIGS. 8A through 8E, in accordance with an embodiment of forming trenches, which may be used to recess electrodes of a thyristor memory device (900 of FIG. 9), a SOI substrate 56 may initially be coated with photoresist and then photolithographically processed to define a patterned photoresist 120 with sidewalls 122. The sidewalls may define a window to expose a region 123 of semiconductor material 60. In a particular embodiment, semiconductor material of layer 60 comprises silicon. In an optional embodiment, an additional insulating layer 121 such as oxide or nitride might also be disposed over silicon layer 60. The depth of insulating material 121 may assist formation of the electrodes to establish with a height therefore that will be above the surface of the silicon layer 60.

Moving forward with reference to FIG. 8B, an exposed portion 123 of silicon layer 60 may be etched using, for example, an anisotropic etch to remove the exposed silicon as defined by the opening in the patterned photoresist 120. In the optional aspect, the etch might first remove exposed regions of the insulating material 121 and, secondly and perhaps in a continuous in-situ etch process with the first, then remove the exposed regions of the silicon layer 60. In a particular example, where the semiconductor material 60 of the SOI substrate 56 may comprises a thickness of 50 nanometers, for example, the etch may remove approximately 20 nanometers of silicon to define floor 126 of the trench with 30 nanometers of silicon therebelow to the buried oxide 58. Again, it will be understood that such dimensions for the trench and thickness of the silicon material may be representative of merely one exemplary embodiment and that alternative embodiments may use different dimensions for the silicon and trench.

Moving forward with reference to FIGS. 8C and 8D, after forming the trench, a dielectric may be conformally layered over the semiconductor material 60 and conformal to its sidewalls 124 and floor 126. In a particular embodiment, the conformal layer of dielectric 127 may comprise an oxide and may be grown by a thermal gate-ox process. It will be understood, that during such oxide formation a portion of the silicon may be consumed by the thermal oxidation so as to reduce its thickness between the floor of the trench 126 and the surface of the buried oxide 58. After lining the trench with the dielectric 127, poly-silicon 128 may be deposited with a thickness sufficient for filling and exceeding the depth of the trench as shown in FIG. 8D.

Referencing FIG. 8E, a planerization procedure such as a chemical mechanical polishing process may be used to planerize and remove some of the polysilicon until exposing insulating material 127. In accordance with the optional embodiment, the planerization continues until reaching an upper surface of insulating layer 121. This may define gate electrode 130 within the trench with an upper surface 132 the same level as that of dielectric 127. Next, an etch may remove exposed portions of the insulating material 127 and/or also the exposed portions of insulating material 121. Accordingly, electrode 130 may be formed with a height above the surface level of semiconductor material 60′.

Again, referencing FIG. 9, it may be understood that the first and second wordlines 262,274 may be formed as recess electrodes in trenches as just described with reference to FIGS. 8A through 8E. Fabrication of the thyristor memory device 900 might then follow processes as described otherwise herein such as for the embodiments for the thyristor memory device 700 of FIG. 7. For example, after the electrodes have been formed within the recessed trenches of the SOI substrate 56, dielectric material may be layered conformally thereover and then anisotropically etched to form spacers 264. And, as before, photoresist may be patterned over other regions of the dielectric material in order to define mask 264″ with a shoulder 35 having a peripheral edge 96 offset from second wordline 274. Definition of the source and drain regions 284,286 about access transistor 273 might then be performed after definition of spacers 264, or alternatively, after definition of N-base 98 and anode/cathode-emitter region 100. Following the implants for the definition of N-base 98, anode/cathode-emitter 100, cathode/anode-emitter 284 and the opposite source/drain region 286; the silicide processing can define salicide regions 110,112,114,116,118 self-aligned to and in exposed surface regions of silicon as defined by the silicide blocking materials 264″,264.

For capacitively coupled thyristor memory cell 900, it may be noted that with the first and second wordlines 262,274 in trenches that the anode-emitter, cathode-emitter and source/drain regions may be described as being raised when viewed relative to the channel regions beneath the electrodes. In accordance with alternative embodiments of the present invention, these raised silicon regions might be formed using alternative epitaxial processes, as will be described more fully below.

In accordance with yet another alternative embodiment of the present invention, as shown in FIG. 10 and in comparison to FIG. 7, additional blocking material may be layered over dielectric layer 64 in order to increase its thickness appropriately so that it may block ions during bombardment for formation of N-base 98. In this particular embodiment, sidewall spacers 64′, may be formed while patterned photoresist covers a portion of the second wordline 74 and also over regions where N-base 98 and anode-emitter 200 may be formed. After defining spacers 64′, the photoresist patterning may be reversed to cover the opposite portion of the second wordline 74, and to cover the source/drain regions about access transistor 73. After such photoresist re-definition, material for mask 364 may be deposited over the previously layered dielectric 64. Next, photo patterning and etching may be used to form the additional blocking material 364 over the lower dielectric layer 64″. While using the increased thickness of blocking material 364 in combination with patterned dielectric 64″ together as an implant mask, ion bombardment may be performed to define N-base 98 beneath the lateral shoulder 235. Next, the anode-emitter implant may be performed while also using the mask of elements 364 and 64″. The second blocking material 364 might then be removed (or alternatively left in place) during epitaxial deposition on regions 200,84,86. Silicide processing might also define salicides 310,312,314,316,318 over respective raised anode-emitter 300, second wordline74, raised source 384, first wordline 62, and raised drain 386 respectively. Known metal interconnects, e.g., might then be formed to couple a voltage reference to the thyristor anode-emitter 200 via interconnect 377 and to couple a bitline 393 to its bitline contacts 318 via conductive interconnects 391,389,387. Dielectric 358 is illustrated generally in FIG. 10 about the various metal layers. It is understood, however, that such material may comprise multiple layers of insulating materials as might be used during the formation of the different metal layers 379,393. Such insulating material 358 might include, for example, spin-on-glass, BPSG, TEOS, etc.

Moving forward with reference to FIG. 11, in accordance with a further embodiment of the present invention, lifetime adjustment impurity species may be implanted into select regions 477 of the thyristor memory cell 1100. The select region 477 may be defined in accordance with photoresist pattern 476 and self-aligned relative to peripheral edge 96 of the silicide blocking mask 64″. Photoresist 476 may be formed over the first and second wordlines 62, 74 and over the source and drain regions of the access transistor 73. Additionally, the photoresist 476 might also be formed over the trench isolation region 212 and portions of anode-emitter 200/300 proximate the isolation trench. The species, energy and angle of incidence during the implant may be selected such that the implant of the lifetime adjustment impurity species may penetrate the interface 101 between anode-emitter 200 and N-base 98, but not interface 99 between N-base 98 and P-base 82. Such lifetime adjustment species may include at least one impurity of the group consisting of germanium, carbon, metal and/or an inert gas of damaging implant that may effect the lifetime of carriers within and across interface 101 of N-base 98 to anode-emitter 200. As shown in this particular embodiment of FIG. 11, the implant impurity species may penetrate a surface region 477 of raised silicon 300 and the surface region portion of a part of N-base 98.

After forming the carrier lifetime adjustment region 477, photoresist 476 may be removed and silicide processing performed similarly as otherwise described herein.

In an alternative embodiment, the lifetime adjustment impurity implant may be performed prior to formation of epitaxial material 300. Accordingly, the implant would affect an upper surface region of anode-emitter 200 and across interface 101 and into a portion of N-base 98. Thereafter, epitaxial and silicide processes could be performed as masked and aligned relative to the epi/silicide blocking effects of dielectric elements 212,64″ and 64′.

In accordance with another embodiment of the present invention, with reference to FIG. 12, patterning of N-base 98 may be performed while using a thickened mask shoulder 435. The shoulder 35 of dielectric mask 64″ may be thickened by forming a conformal layer of additional material thereover with a thickness greater than the width of shoulder 35. After forming the second material over the dielectric mask 64″, the second material may be etched anisotropically to form another spacer 464 over shoulder 35 of dielectric mask 64″. The dielectric mask 64″ and added spacer 464 may be used in combination during an angled implant for the definition of N-base 98 therebelow. Processing might otherwise continue as described herein.

In accordance with a further embodiment of the present invention, referencing FIG. 13A, after forming first spacers 64′, regions associated with access transistors of the semiconductor device may be protected by masking patterned photoresist 574 and a second layer of material layered and then etched anisotropically to define second spacer 564 to thicken the spacer width against a side of the second electrode 74 for a lateral offset appropriate for forming a N-base 98 therebelow (see FIG. 13B).

In an alternative embodiment, the second layer of material may be layered over all of the structures and then etched anisotropically to define spacers from the second layer of material alongside each of the sidewalls of the electrodes. Next, a resist layer may be formed/patterned to protect regions where the widened spacers should be kept. Un-protected spacers formed from the second layer of material may then be removed from around electrode 62 and between electrodes 62,74.

Further referencing FIGS. 13A and 13B, the angled implant for definition of N-base 98 may extend the impurities beneath second spacer 564 and also beneath portion of first spacer 64′ to establish an interface 99 of the N-base therebelow. After forming the N-base, an implant of opposite conductivity may be performed to define anode-emitter 200. Next, epitaxial silicon may be selectively deposited over the exposed silicon regions to form raised structures 300,384,386 over respective anode-emitter 200, cathode-emitter 84 and source/drain 86. Following such epitaxial deposition, sacrificial spacer 564 may be removed and photoresist patterned to define mask 576 with sidewalls that define an opening for exposing portions of the thyristor device, which may overlap a portion of second wordline 74 and a portion of raised silicon 300 of the anode-emitter. While using the patterned photoresist 576 as a mask, lifetime adjustment impurity species may be implanted into regions 577 associated with a portion of the anode-emitter and across its interface 101 to a portion of N-base 98. The impurity implant might also embed a portion 579 of the polysilicon of second wordline 74. It will be noted that first spacer 64′ having a peripheral edge extending across a portion of N-base 98, might thus prevent the implant of the lifetime adjustment impurities from overlapping interface 99 from the N-base 98 to P-base 82. Accordingly, while the lifetime adjustment implant region 577 may affect leakage characteristics of interface 101 from N-base 98 to anode-emitter 200; the integrity of its opposite interface 99 might otherwise be preserved.

Moving forward in accordance with a further embodiment of the present invention, with reference to FIG. 14, carrier lifetime adjustment species or junction leakage implant may be positioned at an alternative interface region 677 between anode-emitter 600 and N-base 398. After forming an N-base region 398 to extend beneath a portion of the lateral shoulder 35 of dielectric mask 64″, an opposite conductivity shallow implant may be performed to form shallow anode-emitter 600 in N-well 398. Accordingly, by such shallow implant, an interface between anode-emitter 600 and N-base 398 may extend laterally to isolation trench 212. After the shallow implant, photoresist may be layered and patterned to define mask 676 over the majority of the thyristor memory cell structure. Sidewalls 677 of the mask may define an opening for establishing regions in which to implant the carrier lifetime (or leakage adjustment) species. The implant may use an energy level sufficient to embed the species into a buried implant region 679 that overlaps the interface between anode-emitter 600 and N-base 398 and at a lateral position proximate isolation trench 212. This leakage implant may be performed using a substantially orthogonal angle of incidence so as to form implant region 679 substantially aligned relative to sidewall 677 of mask 676. After defining the lifetime adjustment species region 679, mask 676 may be removed and epitaxial material 300 may be formed selectively over the exposed silicon regions of the SOI substrate 59. Silicide might also be formed thereover similarly as described earlier herein.

In accordance with yet another embodiment of the present invention, with reference to FIG. 15, dielectric of the isolation trench 212 may be removed for lowering its level and re-defining an alternative depth or floor 612 of the isolation trench. The floor 612 of the isolation trench may be lowered sufficiently to expose ends 622 of anode-emitter 600 facing the trench and laterally distant second wordline 74. Silicide may then be formed to diffuse metal into exposed surface regions of the silicon, including the ends 622 facing the newly defined isolation trench. The metal diffusion might also overlap the interface between the shallow implant anode-emitter 600 and N-base 398. As illustrated in FIG. 15, various alternative depths 612 might be formed for the isolation trench.

While certain exemplary features of the embodiments of the invention have been illustrated and described above, many modifications, substitutions, changes and equivalents may be available to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such embodiments and changes as fall within the spirit of this invention. 

1. A memory device comprising: semiconductor material; a thyristor comprising a first base region contiguous to a second base region, the first and the second base regions being in the semiconductor material and each having a portion contiguous to and defining in part a top surface of the semiconductor material, the thyristor further comprising a first emitter and a second emitter, at least a portion of the first emitter being contiguous to and defining an upper surface of semiconductor material of an elevation above the top surface defined by the portion(s) of the first and the second base regions; and an electrode disposed above the top surface and laterally displaced from the portion of the first emitter, the electrode being capacitively coupled to at least one of the first and the second base regions.
 2. The device of claim 1, wherein the portion(s) of the first the second base regions for the top surface and the at least a portion of the first emitter define at least in part a floor and a wall to a trench structure for the semiconductor material, and the electrode is disposed within the trench in insulated relationship with respect to the semiconductor material; the device further comprising dielectric disposed between the electrode and the top surface that is defined in part by the at least one of the first and the second base regions.
 3. The device of claim 2, wherein the dielectric further defines in part an insulating spacer disposed laterally between a sidewall of the electrode and the portion of the first emitter that defined at least in part the wall for the trench.
 4. The device of claim 1, wherein the portion(s) of the first the second base regions for the top surface and the at least a portion of the first emitter define at least in part a floor and a side wall respectively for a trench defined in the semiconductor material, and the electrode is disposed in insulated relationship to the semiconductor material at least partially recessed within the trench.
 5. The device of claim 4, further comprising dielectric disposed between the electrode and the top surface that is defined in part by the at least one of the first and the second base regions for the capacitive coupling of the electrode thereto.
 6. The device of claim 1, further comprising an access transistor having a source, a drain, a channel region disposed between the source and the drain, and a gate operably disposed to control the channel region; wherein one of the source and the drain is connected to the portion of the first emitter; a portion of the channel region defines a top surface of an elevation less than that formed by the surfaces of the respective source and drain regions; and the gate is recessed at least in part within a trench structure defined by the surfaces of the respective channel region, the source region and the drain region.
 7. The device of claim 6, wherein the top surface defined by the portion(s) of the first and the second base regions beneath the electrode and the top surface defined by the portion of the channel region beneath the gate are of substantially a common plane of elevation beneath that for the upper surface for the first emitter.
 8. The device of claim 1, wherein the at least portion of the first emitter for said elevation is defined at least in part by epitaxial deposited silicon.
 9. The device of claim 8, further comprising silicide on at least part of said portion of the first emitter for said elevation. 